126 lines
3.1 KiB
VHDL
126 lines
3.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: EFREI Paris
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-- Engineer: Tunui Franken
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--
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-- Create Date: 2021/10/26
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-- Design Name:
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-- Module Name:
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-- Project Name:
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-- Target Devices: xc7a200tsbg484
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-- Tool versions:
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-- Description:
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--
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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entity fsm is
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port (
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clk : in std_logic;
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rst : in std_logic;
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defaut : in std_logic;
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rouge : out std_logic;
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orange : out std_logic;
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vert : out std_logic);
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end entity fsm;
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architecture RTL of fsm is
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type state_t is (state_rouge, state_orange, state_vert, state_eteint);
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signal state : state_t;
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signal sync_500ms : std_logic;
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signal sync_2s : std_logic;
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signal sync_15s : std_logic;
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begin
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-- Process générant les signaux de synchronisation sync_15s, sync_500ms et sync_2s
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counter : process (clk, rst) is
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begin -- process fsm_p
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if rst = '1' then
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sync_500ms <= '0';
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sync_2s <= '0';
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sync_15s <= '0';
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elsif rising_edge(clk) then
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/* A COMPLETER */
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if count_500ms < 499 then -- a convertir en binaire
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count_500ms <= count_500ms + '1';
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end if;
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end if;
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end process counter;
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-- Process de la machine d'état
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fsm_p : process (clk, rst) is
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begin -- process fsm_p
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if rst = '1' then
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state <= state_orange;
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rouge <= '0';
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orange <= '1';
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vert <= '0';
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elsif rising_edge(clk) then
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case(state) is
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when state_orange =>
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-- sorties
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rouge <= '0';
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orange <= '1';
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vert <= '0';
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-- transitions
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if (defaut = '0' and sync_2s = '1') then
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state <= state_rouge;
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end if;
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if (defaut = '1' and sync_500ms = '1') then
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state <= state_eteint;
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end if;
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when state_vert =>
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-- sorties
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rouge <= '0';
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orange <= '0';
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vert <= '1';
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-- transitions
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if (defaut = '0' and sync_15s = 1) then
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state <= state_orange;
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end if;
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if (defaut = '1' and sync_500ms = 1) then
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state <= state_eteint;
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end if;
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when state_rouge =>
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-- sorties
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rouge <= '1';
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orange <= '0';
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vert <= '0';
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-- transitions
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if (defaut = '0' and sync_15s = '1') then
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state <= state_vert;
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end if;
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if (defaut = '1' and sync_500ms = '1') then
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state <= state_eteint;
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end if;
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when state_eteint =>
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-- sorties
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rouge <= '0';
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orange <= '0';
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vert <= '0';
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-- transitions
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if (defaut = '1' and sync_500ms = '1') then
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state <= state_orange;
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end if;
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when others =>
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-- sorties
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rouge <= '0';
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orange <= '1';
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vert <= '0';
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state <= state_orange;
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end if;
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end process fsm_p;
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end architecture RTL;
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