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-- Company: EFREI Paris
-- Engineer: Tunui Franken
--
-- Create Date: 2021/10/26
-- Design Name:
-- Module Name:
-- Project Name:
-- Target Devices: xc7a200tsbg484
-- Tool versions:
-- Description:
--
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;


entity fsm is
  port (
    clk    : in  std_logic;
    rst    : in  std_logic;
    defaut : in  std_logic;
    rouge  : out std_logic;
    orange : out std_logic;
    vert   : out std_logic);
end entity fsm;

architecture RTL of fsm is
  type state_t is (state_rouge, state_orange, state_vert, state_eteint);
  signal state      : state_t;
  signal sync_500ms : std_logic;
  signal sync_2s    : std_logic;
  signal sync_15s   : std_logic;

begin
  -- Process générant les signaux de synchronisation sync_15s, sync_500ms et sync_2s
  counter : process (clk, rst) is
  begin  -- process fsm_p
    if rst = '1' then
      sync_500ms <= '0';
      sync_2s <= '0';
      sync_15s <= '0';
    elsif rising_edge(clk) then
      /* A COMPLETER */
      if count_500ms < 499 then -- a convertir en binaire
        count_500ms <= count_500ms + '1';
      end if;


    end if;
  end process counter;


  -- Process de la machine d'état
  fsm_p : process (clk, rst) is
  begin  -- process fsm_p
    if rst = '1' then
      state <= state_orange;
      rouge <= '0';
      orange <= '1';
      vert <= '0';
    elsif rising_edge(clk) then
      case(state) is
        when state_orange =>
          -- sorties
          rouge  <= '0';
          orange <= '1';
          vert   <= '0';
          -- transitions
          if (defaut = '0' and sync_2s = '1') then
            state <= state_rouge;
          end if;
          if (defaut = '1' and sync_500ms = '1') then
            state <= state_eteint;
          end if;
        when state_vert =>
          -- sorties
          rouge  <= '0';
          orange <= '0';
          vert   <= '1';
          -- transitions
          if (defaut = '0' and sync_15s = 1) then
            state <= state_orange;
          end if;
          if (defaut = '1' and sync_500ms = 1) then
            state <= state_eteint;
          end if;
        when state_rouge =>
          -- sorties
          rouge  <= '1';
          orange <= '0';
          vert   <= '0';
          -- transitions
          if (defaut = '0' and sync_15s = '1') then
            state <= state_vert;
          end if;
          if (defaut = '1' and sync_500ms = '1') then
            state <= state_eteint;
          end if;
        when state_eteint =>
          -- sorties
          rouge  <= '0';
          orange <= '0';
          vert   <= '0';
          -- transitions
          if (defaut = '1' and sync_500ms = '1') then
            state <= state_orange;
          end if;
        when others =>
          -- sorties
          rouge  <= '0';
          orange <= '1';
          vert   <= '0';
          state <= state_orange;
    end if;
  end process fsm_p;

end architecture RTL;