190 lines
5.8 KiB
VHDL
190 lines
5.8 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company: EFREI Paris
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-- Engineer: Tunui Franken
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--
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-- Create Date: 2021/10/26
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-- Design Name:
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-- Module Name:
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-- Project Name:
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-- Target Devices: xc7a200tsbg484
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-- Tool versions:
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-- Description:
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--
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all; -- Bibliotheque definissant le type unsigned
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-- necessaire pour les additions
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entity fsm is
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generic(sim : std_logic := '0'); -- Si sim = 1, les modulo des compteurs
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-- internes sont plus petits, raccourcissant
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-- ainsi le temps de simulation
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port (
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clk : in std_logic; -- Horloge 1kHz (période 1 ms)
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rst : in std_logic; -- Reset
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defaut : in std_logic; -- Entrée signalant un defaut
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rouge : out std_logic; -- Sortie à 1 pour allumer le feux rouge
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orange : out std_logic; -- Sortie à 1 pour allumer le feux orange
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vert : out std_logic); -- Sortie à 1 pour allumer le feux vert
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end entity fsm;
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architecture RTL of fsm is
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-- Définition du type state_t
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type state_t is (state_rouge, state_orange, state_vert, state_eteint);
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signal state : state_t;
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-- Définition des signaux de synchronisation
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signal sync_500ms : std_logic;
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signal sync_2s : std_logic;
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signal sync_15s : std_logic;
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-- Definition des signaux de compteur
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-- période de front montant de clk = 1ms (1/1kHz) donc
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-- count_500ms compte 500 fronts montant de clk
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-- count_2s compte 4 fronts montant de count_500ms
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-- count_15s compte 30 fronts montant de count_500ms
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signal count_500ms : std_logic_vector(8 downto 0); -- 9 bits pour représenter 500 fronts
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signal count_2s : std_logic_vector(1 downto 0); -- 2 bits pour représenter 4 fronts
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signal count_15s : std_logic_vector(4 downto 0); -- 5 bits pour représenter 30 fronts
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-- Definition des constantes des modulo de compteur
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constant c_500ms : std_logic_vector(8 downto 0) := "111110101"; -- 501 (499 = 111110011)
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constant c_2s : std_logic_vector(1 downto 0) := "11"; -- 3
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constant c_15s : std_logic_vector(4 downto 0) := "11110"; -- 30 (29 = 11101
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-- Modulo pour la Simulation (si sim='1')
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constant c_sim : std_logic_vector(3 downto 0) := "0010"; -- 2 (pourquoi un bus de 4 et pas de 2)
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begin
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-- Process générant les signaux de synchronisation sync_15s, sync_500ms et sync_2s
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counter : process (clk, rst) is
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begin -- process fsm_p
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if rst = '1' then
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sync_500ms <= '0';
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sync_2s <= '0';
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sync_15s <= '0';
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count_500ms <= (others => '0');
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count_15s <= (others => '0');
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count_2s <= (others => '0');
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elsif rising_edge(clk) then
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-- Par défaut les signaux de synchro sont à 0
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sync_500ms <= '0';
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sync_2s <= '0';
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sync_15s <= '0';
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-- Compteur 500ms
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if sim = '0' then
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if count_500ms < c_500ms then
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count_500ms <= std_logic_vector(unsigned(count_500ms) + 1);
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else
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sync_500ms <= '1';
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count_500ms <= (others => '0');
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end if;
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else
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if count_500ms < c_sim then
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count_500ms <= std_logic_vector(unsigned(count_500ms) + 1);
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else
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sync_500ms <= '1';
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count_500ms <= (others => '0');
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end if;
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end if;
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-- Compteur 2s
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if sync_500ms = '1' then
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if count_2s < c_2s then
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count_2s <= std_logic_vector(unsigned(count_2s) + 1);
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else
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sync_2s <= '1';
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count_2s <= (others => '0');
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end if;
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end if;
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-- Compteur 15s
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if sync_500ms = '1' then
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if count_15s < c_15s then
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count_15s <= std_logic_vector(unsigned(count_15s) + 1);
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else
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sync_15s <= '1';
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count_15s <= (others => '0');
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end if;
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end if;
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end if;
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end process counter;
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-- Process de la machine d'état
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fsm_p : process (clk, rst) is
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begin -- process fsm_p
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if rst = '1' then
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state <= state_orange;
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rouge <= '0';
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orange <= '1';
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vert <= '0';
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elsif rising_edge(clk) then
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case(state) is
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when state_rouge =>
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-- sorties
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rouge <= '1';
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orange <= '0';
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vert <= '0';
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-- transitions
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if (defaut = '0' and sync_15s = '1') then
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state <= state_vert;
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end if;
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if (defaut = '1' and sync_500ms = '1') then
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state <= state_eteint;
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end if;
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when state_orange =>
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-- sorties
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rouge <= '0';
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orange <= '1';
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vert <= '0';
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-- transitions
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if (defaut = '0' and sync_2s = '1') then
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state <= state_rouge;
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end if;
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if (defaut = '1' and sync_500ms = '1') then
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state <= state_eteint;
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end if;
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when state_vert =>
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-- sorties
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rouge <= '0';
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orange <= '0';
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vert <= '1';
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-- transitions
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if (defaut = '0' and sync_15s = '1') then
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state <= state_orange;
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end if;
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if (defaut = '1' and sync_500ms = '1') then
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state <= state_eteint;
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end if;
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when state_eteint =>
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-- sorties
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rouge <= '0';
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orange <= '0';
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vert <= '0';
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-- transitions
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if sync_500ms = '1' then
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state <= state_orange;
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end if;
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when others =>
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-- sorties
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rouge <= '0';
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orange <= '1';
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vert <= '0';
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state <= state_orange;
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end case;
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end if;
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end process fsm_p;
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end architecture RTL;
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