efrei/logique-programmable/exercices/vhdl/ctd1-q6.vhd

11 lines
329 B
VHDL

entity comp is
port (
clk : in std_logic;
rst : in std_logic;
e1 : in std_logic_vector(1 downto 0);
e2 : in std_logic;
e3 : in std_logic_vector(2 downto 0);
s1 : out std_logic);
s2 : out std_logic_vector(1 downto 0);
s3 : out std_logic);
end entity comp;