141 lines
4.9 KiB
TeX
141 lines
4.9 KiB
TeX
\documentclass[a4paper,french,12pt]{article}
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\title{Logique Programmable --- CTD2}
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\author{}
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\date{Dernière compilation~: \today{} à \currenttime}
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\usepackage{../styles}
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\usepackage{enumitem}
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\begin{document}
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\maketitle
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\begin{enumerate}
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\item Donner l'acronyme d'EDA\@.
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Donner les 3 étapes du workflow pour configurer un FPGA\@.
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\item Expliquer la différence entre le VHDL de simulation et le VHDL de synthèse.
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Donner le mot clef non synthétisable.
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Le VHDL de simulation n'est pas forcément synthétisable.
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C'est le VHDL algorithmique, de test, etc.
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Le VHDL de synthèse sert à configurer des FPGA\@.
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\texttt{wait} n'est pas synthétisable.
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\item En VHDL, dans l'architecture, à quoi sert un signal~?
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À interconnecter des process.
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\item
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\item
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\item \begin{itemize}
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\item Rappeler les équations logiques d'un demi-additionneur 2 bits.
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Le décrire en VHDL\@.
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\begin{align*}
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\texttt{s} &= \texttt{a} \oplus \texttt{b} \\
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\texttt{cout} &= \texttt{a} \cdot \texttt{b}
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\end{align*}
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\begin{tabular}{cc|cc}
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\toprule
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A & B & S & Cout \\
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\midrule
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0 & 0 & 0 & 0 \\
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0 & 1 & 1 & 0 \\
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1 & 0 & 1 & 0 \\
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1 & 1 & 0 & 1 \\
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\bottomrule
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\end{tabular}
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\begin{lstlisting}[gobble=20]
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity DA is
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port(
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A: in std_logic;
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B: in std_logic;
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S: out std_logic;
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Cout: out std_logic);
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end DA;
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architecture arch_DA of DA is
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begin
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S <= A xor B;
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Cout <= A and B;
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end arch_DA;
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\end{lstlisting}
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Variation avec une clock~:
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\begin{lstlisting}[gobble=20]
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity DA is
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port(
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A: in std_logic;
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B: in std_logic;
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S: out std_logic;
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Cout: out std_logic);
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end DA;
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architecture arch_DA of DA is
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process (rst, clk)
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begin
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if (rst = '1') then
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S <= 0;
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Cout <= 0;
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elsif(rising_edge(clk))
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S <= A xor B;
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Cout <= A and B;
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endif;
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endprocess;
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end arch_DA;
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\end{lstlisting}
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\item Rappeler les équations logiques d'un additionneur complet.
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Le décrire en VHDL à partir de la description d'un demi-additionneur.
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\begin{tabular}{ccc|cc}
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\toprule
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full\_a & full\_b & full\_cin & full\_s & full\_cout \\
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\midrule
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0 & 0 & 0 & 0 & 0 \\
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0 & 0 & 1 & 1 & 0 \\
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0 & 1 & 0 & 1 & 0 \\
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0 & 1 & 1 & 0 & 1 \\
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1 & 0 & 0 & 1 & 0 \\
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1 & 0 & 1 & 0 & 1 \\
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1 & 1 & 0 & 0 & 1 \\
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1 & 1 & 1 & 1 & 1 \\
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\bottomrule
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\end{tabular}
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\begin{align*}
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\texttt{full\_s} &= \texttt{full\_a} \oplus \texttt{full\_b} \oplus \texttt{full\_cin} \\
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\texttt{full\_cout} &= \texttt{full\_a} \cdot \texttt{full\_b} + \texttt{full\_cin} \cdot (\texttt{full\_a} \oplus \texttt{full\_b})
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\end{align*}
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\begin{lstlisting}[gobble=20]
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity DA is
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port(
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full_a: in std_logic;
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full_b: in std_logic;
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full_cin: in std_logic;
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full_s: out std_logic;
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full_cout: out std_logic);
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end DA;
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architecture arch_DA of DA is
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begin
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full_s <= full_a xor full_b xor full_cin;
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full_cout <= full_a and full_b or full_cin and (full_a xor full_b);
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end arch_DA;
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\end{lstlisting}
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\end{itemize}
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\end{enumerate}
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\end{document}
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