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Add TP2 ex 6

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flyingscorpio@pinebookpro 2021-10-25 13:50:24 +02:00
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logique-programmable/exercices/ctd2.tex
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@ -31,6 +31,32 @@
\item
\item
\item \begin{itemize}
\item Rappeler les équations logiques d'un demi-additionneur 2 bits.
Le décrire en VHDL\@.
\begin{align*}
\texttt{s} &= \texttt{a} \oplus \texttt{b} \\
\texttt{cout} &= \texttt{a} \cdot \texttt{b}
\end{align*}
\begin{lstlisting}[gobble=20]
s = a xor b;
cout = a and b;
\end{lstlisting}
\item Rappeler les équations logiques d'un additionneur complet.
Le décrire en VHDL à partir de la description d'un demi-additionneur.
\begin{align*}
\texttt{full\_s} &= (\texttt{full\_a} \oplus \texttt{full\_b}) \oplus \texttt{full\_cin} \\
\texttt{full\_cout} &= \texttt{full\_a} \cdot \texttt{full\_b} + \texttt{full\_cin} \cdot (\texttt{full\_a} \oplus \texttt{full\_b})
\end{align*}
\begin{lstlisting}[gobble=20]
full_s = (full_a xor full_b) xor full_cin;
full_cout = full_a and full_b or full_cin and (full_a xor full_b);
\end{lstlisting}
\end{itemize}
\end{enumerate}
\end{document}