12 lines
329 B
VHDL
12 lines
329 B
VHDL
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entity comp is
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port (
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clk : in std_logic;
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rst : in std_logic;
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e1 : in std_logic_vector(1 downto 0);
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e2 : in std_logic;
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e3 : in std_logic_vector(2 downto 0);
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s1 : out std_logic);
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s2 : out std_logic_vector(1 downto 0);
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s3 : out std_logic);
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end entity comp;
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