64 lines
1.4 KiB
VHDL
64 lines
1.4 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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entity fsm_tb is
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end entity;
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architecture fsm_tb_arch of fsm_tb is
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-- Déclarations
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signal clk_tb : std_logic;
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signal rst_tb : std_logic;
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signal defaut_tb : std_logic;
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signal rouge_tb : std_logic;
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signal orange_tb : std_logic;
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signal vert_tb : std_logic;
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component fsm
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generic(sim : std_logic := '0');
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port (
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clk : in std_logic;
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rst : in std_logic;
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defaut : in std_logic;
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rouge : out std_logic;
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orange : out std_logic;
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vert : out std_logic);
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end component;
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constant clk_period: time := 1 ms; -- inverse de 1kHz
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begin
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fsm_1: entity work.fsm
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port map (
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clk => clk_tb,
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rst => rst_tb,
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defaut => defaut_tb,
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rouge => rouge_tb,
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orange => orange_tb,
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vert => vert_tb);
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STIM: process
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begin
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-- Génération d'une horloge de 1kHz
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clk_tb <= not clk_tb;
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wait for clk_period/2;
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-- Initialisation de rst à 1 et de defaut à 0
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rst_tb <= '1';
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defaut_tb <= '0';
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-- Passer rst à 0 après 4 ms
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wait for 4 ms;
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rst_tb <= '0';
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-- Passer defaut à 1 après 8 secondes
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wait for 8000 ms;
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defaut_tb <= '1';
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-- Passer defaut à 0 après 1 seconde
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wait for 1000 ms;
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defaut_tb <= '0';
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-- Terminer la simulation après 1 seconde
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wait for 1000 ms;
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wait;
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end process;
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end architecture;
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